/*
 * vg_ip_types.h
 *
 *  Created on: 25/set/2018
 *      Author: chessaa
 */

#ifndef VG_IP_TYPES_H_
#define VG_IP_TYPES_H_


#include <stdint.h>

typedef uint32_t vg_ip_fw_reg_t;

#define VG_IP_BF_(x_)	(1<<(x_))

struct vg_ip_fw_cfg_t	//SRSS1002034-01 Rev. B
{
	//typedef vg_drv_palette_t palette_t;
	//enum { palette_entries=255};
	//typedef struct { vg_ip_fw_reg_t p[palette_entries]; } palette_t;

	template<unsigned int S_, unsigned int E_> struct reserved_range { vg_ip_fw_reg_t r_[((E_-S_)+1)/sizeof(vg_ip_fw_reg_t)];};


	vg_ip_fw_reg_t identification; //Identification  register	0x0000	R

	vg_ip_fw_reg_t mode_selector;  //REQ_VIDEO_ANALOG_CFG_010: Mode selector register	0x0004	R/W
		enum mode_selector_code_t { mode_idle, mode_stby, mode_active};

	vg_ip_fw_reg_t video_standard_selector; //REQ_VIDEO_ANALOG_CFG_011: Video standard selector register	0x0008	R/W
	vg_ip_fw_reg_t reserved0;	//Reserved for future use	0x000C	---

	vg_ip_fw_reg_t configuration; //REQ_VIDEO_ANALOG_CFG_012: Configuration register	0x0010	R/W
		enum config_flags_t {
			cfg_reset_value=0,

			cfg_gfx_enable=VG_IP_BF_(0),
			cfg_sc_enable =VG_IP_BF_(1),
			cfg_vid_enable=VG_IP_BF_(3),

			cfg_test_pattern_shift=8,
			cfg_test_pattern_mask=0x7<<cfg_test_pattern_shift,

			cfg_test_pattern_enable=VG_IP_BF_(11),

			cfg_hv_syncs_enable=VG_IP_BF_(13)
		};

	vg_ip_fw_reg_t reserved1; //reserved for future use	0x0014	R

	vg_ip_fw_reg_t graph_video_memory_offset; //Graph video-memory offset register	0x0018	R/W
	vg_ip_fw_reg_t reserved2; //Reserved for future use	0x001C	R

	vg_ip_fw_reg_t scan_video_memory_offset; //Scan video-memory offset register	0x0020	R/W
	vg_ip_fw_reg_t reserved3; //Reserved for future use	0x0024	R

	vg_ip_fw_reg_t graph_window_offset;	//Graph display-window offset register	0x0028	R/W
	vg_ip_fw_reg_t reserved4; //reservedReserved for future use	0x002C	R

	vg_ip_fw_reg_t scan_window_offset; //Scan display-window offset register	0x0030	R/W
	vg_ip_fw_reg_t reserved5; //Reserved for future use	0x0034	R

	vg_ip_fw_reg_t graph_window_size; //Graph display-window size register	0x0038	R/W
	vg_ip_fw_reg_t reserved6; //Reserved for future use	0x003C	R

	vg_ip_fw_reg_t scan_window_size; //Scan display-window size register	0x0040	R/W
	vg_ip_fw_reg_t reserved7; //Reserved for future use	0x0044	R

	vg_ip_fw_reg_t default_background_color; //Default backgorund color register	0x0048	R/W
	vg_ip_fw_reg_t reserved8; //Reserved for future use	0x004C	R

	vg_ip_fw_reg_t graph_memory_stride;
	vg_ip_fw_reg_t reserved9;

	vg_ip_fw_reg_t scan_memory_stride;
	//vg_ip_fw_reg_t reserved10;

	vg_ip_fw_reg_t vmem_offset;


	//reserved_range<0x060, 0x0FFF> reserved11; //Reserved for future use	0x0050..0x00FF
};

struct vg_ip_fw_palet_t
{
	typedef vg_drv_palette_t palette_t;

	palette_t graph_look_up_table; //Graph Look-up-Table	0x1000.. 0x04FF	R/W	7.1.4
	//reserved_range<0x1400, 0x01FFF> reserved12; //Reserved for future use	0x0050..0x00FF
};

#if 0
struct vg_ip_fw_palet_t
{
    palette_t scan_look_ip_table; //Scan Look-up-Table	0x2000     ..0x08FF	R/W
	reserved_range<0x3000,0x30FF> reserved13; //Reserved for future use	0x3000..0x09FF	---	---
};
#endif

extern volatile vg_ip_fw_cfg_t* vg_ip_cfg_;
extern volatile vg_ip_fw_palet_t* vg_ip_graph_palet_;
extern volatile vg_ip_fw_palet_t* vg_ip_sc_palet_;



#endif /* VG_IP_TYPES_H_ */
