#ifndef AESA_IF_TYPES_H
#define AESA_IF_TYPES_H

#include <stdint.h>

#define PAYLOAD_BYTES                       256
#define AESA_RX_CFGMEM_MAX_SIZE             PAYLOAD_BYTES*2+1

// CTI commands
#define CTI_READ_STATUS_CMD                 0x01
#define CTI_READ_STATUS_CMD_SIZE               2
#define CTI_READ_EXTENDED_STATUS_CMD        0x07
#define CTI_READ_EXTENDED_STATUS_CMD_SIZE      2
#define CTI_INIT_LINK_1_CMD                 0x1E
#define CTI_INIT_LINK_2_CMD                 0x1F
#define CTI_INIT_LINK_CMD_SIZE                67
#define CTI_INIT_LINK_PATTERN_SIZE            32
#define CTI_NVM_WRITE_ENABLE_CMD            0x0A
#define CTI_NVM_WRITE_ENABLE_CMD_SIZE          4
#define CTI_TIME_SYNC_CMD                   0x1A
#define CTI_TIME_SYNC_CMD_SIZE                 8
#define CTI_ARRAY_ERROR_LOG_WRITE_CMD       0x0E
#define CTI_ARRAY_ERROR_LOG_WRITE_CMD_SIZE    11

// CTI responses
#define CTI_STATUS_RSP                      0x70
#define CTI_STATUS_RSP_SIZE                    6
#define CTI_IMU_STATUS_RSP                  0x74
#define CTI_IMU_STATUS_RSP_SIZE                2
#define CTI_EXTENDED_STATUS_RSP             0x78
#define CTI_EXTENDED_STATUS_RSP_SIZE          19
#define CTI_ETI_READBACK_RSP                0x7B
#define CTI_INIT_RESPONSE_RSP               0x8E
#define CTI_INIT_RESPONSE_RSP_SIZE            67
#define CTI_INIT_STATUS_RSP                 0x8F
#define CTI_INIT_STATUS_RSP_SIZE              10
#define CTI_INIT_PATTERN_SIZE                 32
#define CTI_TIME_SYNC_STATUS_RSP            0x7C
#define CTI_TIME_SYNC_STATUS_RSP_SIZE          8

// AESA commands
#define AESA_READ_STATUS_CMD                0xAE
#define AESA_READ_STATUS_CMD_SIZE              4
#define AESA_READ_FIRMWARE_STATUS_CMD       0xAF
#define AESA_READ_FIRMWARE_STATUS_CMD_SIZE     2

// AESA responses
#define AESA_STATUS_RSP                     0x80
#define AESA_STATUS_RSP_SIZE                   0
#define AESA_FIRMWARE_STATUS_RSP            0x81
#define AESA_FIRMWARE_STATUS_RSP_SIZE        136
#define AESA_BROADCAST_STATUS_RSP           0x71
#define AESA_BROADCAST_STATUS_RSP_SIZE         7

// RFIF commands
#define RFIF_MODE_CMD                       0x20
#define RFIF_MODE_CMD_SIZE                     9
#define RFIF_READ_STATUS_CMD                0x22
#define RFIF_READ_STATUS_CMD_SIZE              2
#define RFIF_READ_BIT_STATUS_CMD            0x23
#define RFIF_READ_BIT_STATUS_CMD_SIZE          2
#define RFIF_READ_FW_STATUS_CMD             0x24
#define RFIF_READ_FW_STATUS_CMD_SIZE           2
#define RFIF_TIME_SYNC_CMD                  0x25
#define RFIF_TIME_SYNC_CMD_SIZE                8
#define RFIF_TIME_SYNC_PAYLOAD_SIZE            6
#define RFIF_NVM_READ_DATA_CMD              0x2B
#define RFIF_NVM_READ_DATA_CMD_SIZE            8
#define RFIF_NVM_ERASE_DATA_CMD             0x28
#define RFIF_NVM_ERASE_DATA_CMD_SIZE           8
#define RFIF_NVM_WRITE_DATA_CMD             0x29
#define RFIF_NVM_WRITE_DATA_CMD_SIZE          16    //(6+2*N)
#define RFIF_ETI_READ_BACK_CMD              0x37
#define RFIF_ETI_READ_BACK_CMD_SIZE            2
#define RFIF_ATTENUATION_DB_LSB              0.5
#define RF_END_TO_END_TEST_CMD              0xA0
#define RF_END_TO_END_TEST_CMD_SIZE           16

//new add LV
#define RFIF_CFGMEM_READ_DATA_CMD           0x33
#define RFIF_CFGMEM_READ_DATA_CMD_SIZE         6
#define RFIF_CFGMEM_ERASE_DATA_CMD          0x34
#define RFIF_CFGMEM_ERASE_DATA_CMD_SIZE        6
#define RFIF_CFGMEM_WRITE_DATA_CMD          0x36
#define RFIF_CFGMEM_WRITE_DATA_CMD_SIZE     PAYLOAD_BYTES*2+6    //(6+2*N)



// RFIF responses
#define RFIF_STATUS_RSP                     0x62
#define RFIF_STATUS_RSP_SIZE                   9
#define RFIF_FIRMWARE_STATUS_RSP            0x63
#define RFIF_FIRMWARE_STATUS_RSP_SIZE          5
#define RFIF_TIME_SYNC_STATUS_RSP           0x64
#define RFIF_TIME_SYNC_STATUS_RSP_SIZE         8
#define RFIF_BIT_STATUS_RSP                 0x67
#define RFIF_BIT_STATUS_RSP_SIZE               8
#define RFIF_NVM_DATA_RSP                   0x6A
#define RFIF_NVM_DATA_RSP_SIZE              PAYLOAD_BYTES*2+1    //1+2*N

#define RFIF_ETI_READ_BACK_RSP              0x6B
#define RFIF_ETI_READ_BACK_RSP_SIZE            6

//new add LV
#define RFIF_CFGMEM_DATA_RSP                0x69
#define RFIF_CFGMEM_DATA_RSP_SIZE           AESA_RX_CFGMEM_MAX_SIZE+2      //1+2*N


// PLANK commands
#define PLANK_TRC_INITIALISE_CMD            0xC1
#define PLANK_TRC_INITIALISE_CMD_SIZE          3
#define PLANK_READ_STATUS_CMD               0xC2
#define PLANK_READ_STATUS_CMD_SIZE             3
#define PLANK_IBIT_START_CMD                0xC3
#define PLANK_IBIT_START_CMD_SIZE              3
#define PLANK_VTX_CONTROL_CMD               0xC4
#define PLANK_VTX_CONTROL_CMD_SIZE             4
#define PLANK_READ_EXTENDED_STATUS_CMD      0xC7
#define PLANK_READ_EXTENDED_STATUS_CMD_SIZE    3

// PLANK responses
#define PLANK_STATUS_RSP                    0x72
#define PLANK_STATUS_RSP_SIZE                  9
#define PLANK_EXTENDED_STATUS_RSP           0x75
#define PLANK_EXTENDED_STATUS_RSP_SIZE        21

// BEAM calculation command
#define BEAM_CALCULATION_CMD                0x82
#define BEAM_CALCULATION_CMD_SIZE             31
#define SAVE_BEAM_CALCULATION_CMD           0x86
#define SAVE_BEAM_CALCULATION_CMD_SIZE        32
#define INDEX_BEAM_CALCULATION_CMD          0x88
#define INDEX_BEAM_CALCULATION_CMD_SIZE        4
#define BEAM_DIRECTION_FACTOR_LSB       /* 3.05e-5F */(2.0f/0xffff)

// Download Map command
#define DOWNLOAD_MAP_CMD                    0xA8
#define DOWNLOAD_MAP_CMD_SIZE                  4
#define DOWNLOAD_MAP_RSP                    0x7F

// Message size
#define AESA_TX_MESSAGE_MAX_SIZE            (8*1024) /*2048*/
//#define AESA_RX_MESSAGE_MAX_SIZE            4096
#define AESA_RX_MESSAGE_MAX_SIZE            2048



namespace aesa
{

/*
  RFIF Mode Command
*/
typedef enum {
    rfif_operative_mode,
    rfif_cal_mode,
    rfif_cal_det_mode,
    rfif_rbt1_mode,
    rfif_rbt2_mode
} rfif_mode_t;

typedef enum {
    guard_sel_1,
    guard_sel_2,
    guard_sel_3,
    guard_sel_4
} rfif_guard_sel_t;

typedef enum {
    tx_open,
    tx_close
} tx_sample_t;

typedef enum {
    up,
    down
} up_down_t;

typedef enum {
    off,
    on
} off_on_t;

typedef struct {
    rfif_mode_t      mode;
    rfif_guard_sel_t guard_sel;
    off_on_t         radiation_on;
    tx_sample_t      tx_sample;
    up_down_t        tx_rx_guard_sel;
    up_down_t        guard_cal_sel;
    up_down_t        cal_sel_a;
    up_down_t        cal_sel_b;
    off_on_t         detector_on_off;
    off_on_t         amp_cal;
    uint8_t          attenuator;
    uint16_t         tx_frequency;
    uint16_t         rx_frequency;
} rfif_mode_command_t;

/*
  Plank Vtx Control Command
*/
typedef struct {
    union {
        uint8_t raw;
        struct {
            uint8_t spare_0         : 1;
            uint8_t control_bits    : 3;
            uint8_t spare_1         : 4;
        } bit;
    } byte_0;
} plank_vtx_control_t;

/*
  Beam Calculation Command
*/
typedef struct {
    uint16_t tx_freq;                       // MHz
    uint16_t rx_freq;                       // MHz
    float    tx_u;                          // u
    float    tx_v;                          // v
    float    rx_u;                          // u
    float    rx_v;                          // v
    uint16_t tx_ctrl_state_index;           // 0..2031
    uint8_t  tx_enable_pattern_index;       // 0..255
    uint16_t rx_ctrl_state_index;           // 0..2031
    uint8_t  rx_enable_pattern_index;       // 0..255
    float    guard_rx_u;                    // u
    float    guard_rx_v;                    // v
    uint16_t guard_rx_ctrl_state_index;     // 0..2031
    uint8_t  guard_rx_enable_pattern_index; // 0..15
    uint16_t sync_divisor;                  // 188..280
    uint8_t  duty_ratio;                    // 0..255
} beam_calculation_t;

/*
  Save Beam Calculation Command
*/
typedef struct {
    uint8_t            beam_index;
    beam_calculation_t beam_data;
} save_beam_calculation_t;

/*
  RF End-To-End Command
*/
typedef enum {
    test_trc_tx_array_test,
    test_trc_tx_plank_test,
    test_trc_rx_array_test,
    test_trc_rx_plank_test
} rf_ete_test_mode_t;

typedef struct {
    rf_ete_test_mode_t test_mode;
    uint8_t            test_plank_id;
    uint8_t            test_trc_id;
    uint8_t            test_trc_gain;
    uint8_t            test_trc_phase;
    uint8_t            first_list_plank_id;
    uint8_t            first_list_trc_id;
    uint8_t            last_list_plank_id;
    uint8_t            last_list_trc_id;
    uint8_t            list_trc_gain;
    uint8_t            list_trc_phase;
    uint16_t           timeout;
    uint8_t            plank_vtx_bcm_ctrl;
} rf_end_to_end_t;

/*
  CTI Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        struct {
            uint8_t coding_error                 : 1;
            uint8_t crc_error                    : 1;
            uint8_t cti_flash_ibit_fail          : 1;
            uint8_t nvm_config_write_complete    : 1;
            uint8_t flash_config_memory_error    : 1;
            uint8_t cti_fram_ibit_error          : 1;
            uint8_t spare                        : 1;
            uint8_t cti_fram_memory_error        : 1;
        } bit;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t tx_rx_pulse_width_error      : 1;
            uint8_t tx_rx_duty_ratio_error       : 1;
            uint8_t cti_factory_image_active     : 1;
            uint8_t cmd_link1_message_fail       : 1;
            uint8_t cmd_link2_message_fail       : 1;
            uint8_t px_uv_beam_pointing_cmd_error: 1;
            uint8_t spare                        : 1;
            uint8_t array_err_log_checksum_error : 1;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        struct {
            uint8_t spare_0                      : 4;
            uint8_t rf_end_to_end_test_complete  : 1;
            uint8_t rf_end_to_end_test_error     : 1;
            uint8_t spare_1                      : 1;
            uint8_t redundant_link_lost          : 1;
        } bit;
    } byte_2;
    union {
        uint8_t raw;
        int8_t cti_temperature;
    } byte_3;
} cti_status_t;

/*
  CTI Extended Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        uint8_t cti_fw_ver_minor_rev;
    } byte_0;
    union {
        uint8_t raw;
        uint8_t cti_fw_ver_major_rev;
    } byte_1;
    union {
        uint8_t raw;
        struct {
            uint8_t command_data_1_lost          : 1;
            uint8_t command_data_2_lost          : 1;
            uint8_t clock_1_lost                 : 1;
            uint8_t clock_2_lost                 : 1;
            uint8_t cti_rxn_1_lost               : 1;
            uint8_t cti_rxn_2_lost               : 1;
            uint8_t spare                        : 2;
        } bit;
    } byte_2;
    union {
        uint8_t raw;
        struct {
            uint8_t prgn_fdbck_pin_open          : 1;
            uint8_t reset_has_occurred           : 1;
            uint8_t vss_status_error             : 1;
            uint8_t cti_temp_sens_comm_err       : 1;
            uint8_t ctrl_dc_vol_bit_adc_comm_err : 1;
            uint8_t single_event_upset_detected  : 1;
            uint8_t factory_image_active         : 1;
            uint8_t atti_eti_cti_fram_ibit_fail  : 1;
        } bit;
    } byte_3;
    union {
        uint8_t raw;
        struct {
            uint8_t quadrant_1_vrx_fail          : 1;
            uint8_t quadrant_2_vrx_fail          : 1;
            uint8_t quadrant_3_vrx_fail          : 1;
            uint8_t quadrant_4_vrx_fail          : 1;
            uint8_t mcu_ps_fault                 : 1;
            uint8_t rfif_ps_fault                : 1;
            uint8_t spare                        : 2;
        } bit;
    } byte_4;
    union {
        uint8_t raw;
        uint8_t minus_5_vss_supply;
    } byte_5;
    union {
        uint8_t raw;
        uint8_t _1_8_pll_supply;
    } byte_6;
    union {
        uint8_t raw;
        uint8_t _1_8_vccio_supply;
    } byte_7;
    union {
        uint8_t raw;
        uint8_t _0_95_cti_fpga_supply;
    } byte_8;
    union {
        uint8_t raw;
        uint8_t _3_0_cti_fpga_supply;
    } byte_9;
    union {
        uint8_t raw;
        uint8_t cti_3_3_motherboard_supply;
    } byte_10;
    union {
        uint8_t raw;
        uint8_t reserved_for_imu;
    } byte_11;
    union {
        uint8_t raw;
        uint8_t cti_temperature;
    } byte_12;
    union {
        uint8_t raw;
        uint8_t reserved_for_imu;
    } byte_13;
    union {
        uint8_t raw;
        uint8_t reserved_for_imu;
    } byte_14;
    union {
        uint8_t raw;
        uint8_t reserved_for_future_use;
    } byte_15;
    union {
        uint8_t raw;
        uint8_t reserved_for_future_use;
    } byte_16;
} cti_extended_status_t;

/*
  CTI INIT Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        uint8_t init_status;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t init_type : 3;
            uint8_t spare     : 5;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        uint8_t spare;
    } byte_2;
    union {
        uint8_t raw;
        uint8_t init_module_id;
    } byte_3;
    union {
        uint8_t raw;
        uint8_t init_rev_id_1;
    } byte_4;
    union {
        uint8_t raw;
        uint8_t init_rev_id_2;
    } byte_5;
    union {
        uint8_t raw;
        uint8_t init_rev_id_3;
    } byte_6;
    union {
        uint8_t raw;
        uint8_t spare;
    } byte_7;
} cti_init_status_t;

/*
  PLANK Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        uint8_t plank_id;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t cti_message_coding_error     : 1;
            uint8_t cti_message_crc_error        : 1;
            uint8_t flash_beam_calc_ibit_error   : 1;
            uint8_t flash_fram_config_write_done : 1;
            uint8_t flash_fram_config_write_error: 1;
            uint8_t flash_local_data_ibit_error  : 1;
            uint8_t plank_factory_image_active   : 1;
            uint8_t plank_reset_has_occurred     : 1;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        struct {
            uint8_t trc_init_complete            : 1;
            uint8_t plank_fpga_suspected_seu     : 1;
            uint8_t plank_rxn_from_cti_not_active: 1;
            uint8_t plank_rxn_watchdog_tripped   : 1;
            uint8_t plank_rxn_watchdog_ibit_error: 1;
            uint8_t comms_watchdog_ibit_error    : 1;
            uint8_t inlet_temp_sens_comms_error  : 1;
            uint8_t outlet_temp_sens_comms_error : 1;
        } bit;
    } byte_2;
    union {
        uint8_t raw;
        struct {
            uint8_t vdd_supply_good              : 1;
            uint8_t vdd_bus_supply_good          : 1;
            uint8_t vtx_bcm_enabled              : 1;
            uint8_t vtx_mpa_power_good           : 1;
            uint8_t vtx_cvcc_hpa_no_out_voltage  : 1;
            uint8_t vtx_bcm1_no_out_voltage      : 1;
            uint8_t vtx_bcm2_no_out_voltage      : 1;
            uint8_t vtx_cvcc_mpa_no_out_voltage  : 1;
        } bit;
    } byte_3;
    union {
        uint8_t raw;
        int8_t inlet_plank_temperature;
    } byte_4;
    union {
        uint8_t raw;
        int8_t outlet_plank_temperature;
    } byte_5;
    union {
        uint8_t raw;
        uint8_t spare;
    } byte_6;
    union {
        uint8_t raw;
        uint8_t spare;
    } byte_7;
//    union {
//        uint8_t raw;
//        struct {
//            uint8_t plank_link_sts_coding_error  : 1;
//            uint8_t plank_link_sts_response_tout : 1;
//            uint8_t plank_nvm_memory_error       : 1;
//            uint8_t plank_fail_establish_error   : 1;
//            uint8_t plank_redundant_link_error   : 1;
//            uint8_t plank_id_error               : 1;
//            uint8_t spare                        : 2;
//        } bit;
//    } byte_8;
} plank_status_t;

/*
  PLANK Extended Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        uint8_t plank_id;
    } byte_0;
    union {
        uint8_t raw;
        uint8_t fw_ver_minor_rev;
    } byte_1;
    union {
        uint8_t raw;
        uint8_t fw_ver_major_rev;
    } byte_2;
    union {
        uint8_t raw;
        uint8_t plank_beam_table_rev;
    } byte_3;
    union {
        uint8_t raw;
        uint8_t plank_nvm_rev;
    } byte_4;
    union {
        uint8_t raw;
        struct {
            uint8_t clk_and_data_link_fault      : 1;
            uint8_t clk_and_spare_link_fault     : 1;
            uint8_t spare_and_data_link_fault    : 1;
            uint8_t plank_rxn_link_fault         : 1;
            uint8_t spare_as_plank_rxn_link_fault: 1;
            uint8_t input_vtx_supply_present     : 1;
            uint8_t input_vrx_supply_present     : 1;
            uint8_t progn_fbck_pin_open_circuit  : 1;
        } bit;
    } byte_5;
    union {
        uint8_t raw;
        struct {
            uint8_t wdog_dac_comms_error         : 1;
            uint8_t pca_config                   : 2;
            uint8_t fram_ibit_error              : 1;
            uint8_t ctrl_dc_v_bit_adc_comms_error: 1;
            uint8_t power_dev_temp_sens_comms_err: 1;
            uint8_t inlet_temp_sens_comms_error  : 1;
            uint8_t outlet_temp_sens_comms_error : 1;
        } bit;
    } byte_6;
    union {
        uint8_t raw;
        uint8_t _1v2_supply_bit_adc;
    } byte_7;
    union {
        uint8_t raw;
        uint8_t _1v8_supply_bit_adc;
    } byte_8;
    union {
        uint8_t raw;
        uint8_t _2v5_supply_bit_adc;
    } byte_9;
    union {
        uint8_t raw;
        uint8_t _3v3_vdd_supply_bit_adc;
    } byte_10;
    union {
        uint8_t raw;
        uint8_t mpa_vtx_supply_bit_adc;
    } byte_11;
    union {
        uint8_t raw;
        uint8_t vtx_bit_adc;
    } byte_12;
    union {
        uint8_t raw;
        uint8_t n3v3_supply_bit_adc;
    } byte_13;
    union {
        uint8_t raw;
        uint8_t n5v0_supply_bit_adc;
    } byte_14;
    union {
        uint8_t raw;
        int8_t inlet_temperature;
    } byte_15;
    union {
        uint8_t raw;
        int8_t outlet_temperature;
    } byte_16;
    union {
        uint8_t raw;
        int8_t power_temperature;
    } byte_17;
    union {
        uint8_t raw;
        uint8_t spare;
    } byte_18;
    union {
        uint8_t raw;
        uint8_t spare;
    } byte_19;
//    union {
//        uint8_t raw;
//        struct {
//            uint8_t plank_link_sts_coding_error  : 1;
//            uint8_t plank_link_sts_response_tout : 1;
//            uint8_t plank_nvm_memory_error       : 1;
//            uint8_t plank_fail_establish_error   : 1;
//            uint8_t plank_redundant_link_error   : 1;
//            uint8_t plank_id_error               : 1;
//            uint8_t spare                        : 2;
//        } bit;
//    } byte_20;
} plank_extended_status_t;

/*
  AESA Broadcast Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        struct {
            uint8_t plank_1_response_error  : 1;
            uint8_t plank_2_response_error  : 1;
            uint8_t plank_3_response_error  : 1;
            uint8_t plank_4_response_error  : 1;
            uint8_t plank_5_response_error  : 1;
            uint8_t plank_6_response_error  : 1;
            uint8_t plank_7_response_error  : 1;
            uint8_t plank_8_response_error  : 1;
        } bit;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t plank_9_response_error  : 1;
            uint8_t plank_10_response_error : 1;
            uint8_t plank_11_response_error : 1;
            uint8_t plank_12_response_error : 1;
            uint8_t plank_13_response_error : 1;
            uint8_t plank_14_response_error : 1;
            uint8_t plank_15_response_error : 1;
            uint8_t plank_16_response_error : 1;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        struct {
            uint8_t plank_17_response_error : 1;
            uint8_t plank_18_response_error : 1;
            uint8_t plank_19_response_error : 1;
            uint8_t plank_20_response_error : 1;
            uint8_t plank_21_response_error : 1;
            uint8_t plank_22_response_error : 1;
            uint8_t plank_23_response_error : 1;
            uint8_t plank_24_response_error : 1;
        } bit;
    } byte_2;
    union {
        uint8_t raw;
        struct {
            uint8_t plank_25_response_error : 1;
            uint8_t plank_26_response_error : 1;
            uint8_t plank_27_response_error : 1;
            uint8_t plank_28_response_error : 1;
            uint8_t plank_29_response_error : 1;
            uint8_t plank_30_response_error : 1;
            uint8_t plank_31_response_error : 1;
            uint8_t plank_32_response_error : 1;
        } bit;
    } byte_3;
    union {
        uint8_t raw;
        struct {
            uint8_t spare                   : 7;
            uint8_t rfif_response_error     : 1;
        } bit;
    } byte_4;
} aesa_broadcast_status_t;

/*
  CTI ETI Readback Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        uint8_t eti_byte_0;
    } byte_0;
    union {
        uint8_t raw;
        uint8_t eti_byte_1;
    } byte_1;
    union {
        uint8_t raw;
        uint8_t eti_byte_2;
    } byte_2;
    union {
        uint8_t raw;
        uint8_t atti_byte_0;
    } byte_3;
    union {
        uint8_t raw;
        uint8_t atti_byte_1;
    } byte_4;
    union {
        uint8_t raw;
        uint8_t atti_byte_2;
    } byte_5;
} cti_eti_readback_status_t;

/*
  PLANK TRCx Status Response Message (part of AESA Status Response)
*/
typedef struct {
    union {
        uint8_t raw;
        struct {
            uint8_t trc1_comm_fault   : 1;
            uint8_t trc1_other_fault  : 1;
            uint8_t trc2_comm_fault   : 1;
            uint8_t trc2_other_fault  : 1;
            uint8_t trc3_comm_fault   : 1;
            uint8_t trc3_other_fault  : 1;
            uint8_t trc4_comm_fault   : 1;
            uint8_t trc4_other_fault  : 1;
        } bit;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t trc5_comm_fault   : 1;
            uint8_t trc5_other_fault  : 1;
            uint8_t trc6_comm_fault   : 1;
            uint8_t trc6_other_fault  : 1;
            uint8_t trc7_comm_fault   : 1;
            uint8_t trc7_other_fault  : 1;
            uint8_t trc8_comm_fault   : 1;
            uint8_t trc8_other_fault  : 1;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        struct {
            uint8_t trc9_comm_fault   : 1;
            uint8_t trc9_other_fault  : 1;
            uint8_t trc10_comm_fault  : 1;
            uint8_t trc10_other_fault : 1;
            uint8_t trc11_comm_fault  : 1;
            uint8_t trc11_other_fault : 1;
            uint8_t trc12_comm_fault  : 1;
            uint8_t trc12_other_fault : 1;
        } bit;
    } byte_2;
    union {
        uint8_t raw;
        struct {
            uint8_t trc13_comm_fault  : 1;
            uint8_t trc13_other_fault : 1;
            uint8_t trc14_comm_fault  : 1;
            uint8_t trc14_other_fault : 1;
            uint8_t trc15_comm_fault  : 1;
            uint8_t trc15_other_fault : 1;
            uint8_t trc16_comm_fault  : 1;
            uint8_t trc16_other_fault : 1;
        } bit;
    } byte_3;
    union {
        uint8_t raw;
        struct {
            uint8_t trc17_comm_fault  : 1;
            uint8_t trc17_other_fault : 1;
            uint8_t trc18_comm_fault  : 1;
            uint8_t trc18_other_fault : 1;
            uint8_t trc19_comm_fault  : 1;
            uint8_t trc19_other_fault : 1;
            uint8_t trc20_comm_fault  : 1;
            uint8_t trc20_other_fault : 1;
        } bit;
    } byte_4;
} plank_trcx_status_t;

/*
  AESA Firmware Status Response Message
*/
#define MAX_NUMBER_OF_PLANKS 32
typedef struct {
    uint8_t major;
    uint8_t minor;
} maj_min_version_t;

typedef struct {
    uint8_t beam_table;
    uint8_t nvm;
} plank_bt_nvm_version_t;

typedef struct {
    maj_min_version_t      cti_fw_version;
    maj_min_version_t      plank_fw_version[MAX_NUMBER_OF_PLANKS];
} aesa_fw_sts_1_t;

typedef struct {
    maj_min_version_t      cti_nvm_version;
    plank_bt_nvm_version_t plank_bt_nvm_version[MAX_NUMBER_OF_PLANKS];
} aesa_fw_sts_2_t;

typedef struct {
    aesa_fw_sts_1_t aesa_fw_status_1;
    aesa_fw_sts_2_t aesa_fw_status_2;
} aesa_firmware_status_t;

/*
  RFIF Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        struct {
            uint8_t modes           : 3;
            uint8_t spare           : 1;
            uint8_t guard_sel       : 2;
            uint8_t health_status   : 1;
            uint8_t warning_status  : 1;
        } bit;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t tx_sample       : 1;
            uint8_t tx_rx_guard_sel : 1;
            uint8_t guard_cal_sel   : 1;
            uint8_t cal_sel_a       : 1;
            uint8_t cal_sel_b       : 1;
            uint8_t detector_on_off : 1;
            uint8_t cti_crc_error   : 1;
            uint8_t amp_cal         : 1;
        } bit;
    } byte_1;
    union {
        uint8_t raw;                            //icd document//rfif update document
        struct {
            uint8_t attenuator       : 6;
            uint8_t cti_coding_error : 1;       //spare//cti_coding_error
            uint8_t spare            : 1;       //spare//consistency check
        } bit;
    } byte_2;
    union {
        int8_t temperature_t1;
    } byte_3;
    union {
        int8_t temperature_t2;
    } byte_4;
    union {
        uint8_t raw;
        struct {
            //rfif update document
            uint8_t rfif_rxn1_lost      : 1;
            uint8_t rfif_rxn2_lost      : 1;
            uint8_t cti_crc_error       : 1;
            uint8_t cti_coding_error    : 1;
            uint8_t spare               : 2;
            uint8_t cfgm_timeout_fail   : 1;
            uint8_t cfgm_busy           : 1;
            //icd document
            /*
            uint8_t rfif_rxn1_lost  : 1;
            uint8_t rfif_rxn2_lost  : 1;
            uint8_t spare           : 6;
            */
        } bit;
    } byte_5;
} rfif_status_t;

/*
  RFIF Bit Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        struct {
            uint8_t detector_tp1   : 1;
            uint8_t detector_tp2   : 1;
            uint8_t detector_tp3   : 1;
            uint8_t detector_tp4   : 1;
            uint8_t detector_tp5   : 1;
            uint8_t detector_tp6   : 1;
            uint8_t detector_tp7   : 1;
            uint8_t detector_tp8   : 1;
        } bit;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t detector_tp12  : 1;
            uint8_t detector_tp15  : 1;
            uint8_t detector_tp16  : 1;
            uint8_t detector_tp13  : 1;
            uint8_t detector_tp14  : 1;
            uint8_t spare          : 3;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        struct {
            uint8_t temp_warning_t1: 1;
            uint8_t temp_warning_t2: 1;
            uint8_t rxn1_missing   : 1;
            uint8_t rxn2_missing   : 1;
            uint8_t clk1_missing   : 1;
            uint8_t clk2_missing   : 1;
            uint8_t rfif_data1_lost: 1;
            uint8_t rfif_data2_lost: 1;
        } bit;
    } byte_2;
    union {
        uint8_t raw;
        struct {
            uint8_t temp_failure_t1: 1;
            uint8_t temp_failure_t2: 1;
            uint8_t volt_logic_fail: 1;
            uint8_t volt_act_fail  : 1;
            uint8_t volt_inp_fail  : 1;
            uint8_t over_duty_test : 1;
            uint8_t pa_overcurr_hp : 1;
            uint8_t pa_overcurr_lp : 1;
        } bit;
    } byte_3;
    union {
        uint8_t raw;
        struct {
            uint8_t cti_coding_err : 1;
            uint8_t cti_crc_err    : 1;
            uint8_t msg_cnt_err    : 1;
            uint8_t rxn_missing    : 1;
            uint8_t spare_0        : 1;
            uint8_t rfif_data_lost : 1;
            uint8_t cmd_mismatch   : 1;
            uint8_t spare_1        : 1;
        } bit;
    } byte_4;
    union {
        uint8_t raw;
        struct {
            uint8_t boot_locnvm_err: 1;
            uint8_t boot_remnvm_err: 1;
            uint8_t boot_volt_warn : 1;
            uint8_t spare          : 3;
            uint8_t over_duty      : 1;
            uint8_t over_pulse     : 1;
        } bit;
    } byte_5;
//    union {
//        uint8_t raw;
//        struct {
//            uint8_t rfif_cod_err   : 1;
//            uint8_t rfif_resp_tout : 1;
//            uint8_t spare          : 6;
//        } bit;
//    } byte_6;
} rfif_bit_status_t;

/*
  RFIF Firmware Status Response Message
*/
typedef struct {
    union {
        uint8_t fw_version;
    } byte_0;
    union {
        uint8_t fw_release;
    } byte_1;
    union {
        uint8_t act_board_cfg;
    } byte_2;
    union {
        uint8_t rfif_cfg;
    } byte_3;
    union {
        uint8_t raw;
        struct {
            uint8_t cti_crc_error    : 1;
            uint8_t cti_coding_error : 1;
            uint8_t spare            : 6;
        } bit;
    } byte_4;
} rfif_fw_status_t;

/*
  RFIF Time Sync Status Response Message
*/
typedef struct {
    union {
        uint8_t raw;
        uint8_t delta_time;
    } byte_0;
    union {
        uint8_t raw;
        uint8_t delta_time;
    } byte_1;
    union {
        uint8_t raw;
        uint8_t delta_time;
    } byte_2;
    union {
        uint8_t raw;
        uint8_t delta_time;
    } byte_3;
    union {
        uint8_t raw;
        uint8_t delta_time;
    } byte_4;
    union {
        uint8_t raw;
        uint8_t delta_time;
    } byte_5;
    union {
        uint8_t raw;
        struct {
            uint8_t rfif_cod_err   : 1;
            uint8_t rfif_resp_tout : 1;
            uint8_t spare          : 6;
        } bit;
    } byte_6;
} rfif_time_sync_status_t;

/*
  CTI Init Response Message
*/
typedef struct {
    uint8_t init_message_id;
    uint8_t init_256_bit_code1[CTI_INIT_PATTERN_SIZE];
    uint8_t init_256_bit_code2[CTI_INIT_PATTERN_SIZE];
} cti_init_response_message_t;

/*
  RFIF Eti Readback Status Response Message
*/
#define RFIF_ETI_NUM_OF_BYTES   3
#define RFIF_ATTI_NUM_OF_BYTES  3
typedef struct {
    uint8_t eti[RFIF_ETI_NUM_OF_BYTES];
    uint8_t atti[RFIF_ATTI_NUM_OF_BYTES];
    union {
        uint8_t raw;
        struct {
            uint8_t rfif_cod_err   : 1;
            uint8_t rfif_resp_tout : 1;
            uint8_t spare          : 6;
        } bit;
    } byte_6;
} rfif_eti_readback_status_t;

/*
  Download Map Trc Status data structure
*/
#define TRC_TEMPERATURE_LSB   0.6127F
typedef struct {
    union {
        uint8_t raw;
        uint8_t trc_id;
    } byte_0;
    union {
        uint8_t raw;
        struct {
            uint8_t trc_resp_parity_err      : 1;
            uint8_t trc_rxn_wdog_fault       : 1;
            uint8_t trc_no_response          : 1;
            uint8_t trc_supp_fault_res_occur : 1;
            uint8_t trc_init_fault           : 1;
            uint8_t trc_map_status           : 2;
            uint8_t trc_crc_err_prev_cmd     : 1;
        } bit;
    } byte_1;
    union {
        uint8_t raw;
        uint8_t trc_response_data;
    } byte_2;
} dwl_map_trc_status_t;

} //namespace

#endif // COMMON_H
