#ifndef GRIFO_FW_ADDRESSES_H
#define GRIFO_FW_ADDRESSES_H

/*
 * FPGA function mapping:
 */

namespace grifo_fw
{

enum fpga_map_t
{
    FPGA_SRIO_NODE_ID   =0x16,
    FPGA_SRIO_HR_NODE_ID   =0x76,

    FPGA_EVENT_INVALID=0xFFFF,  //used to mark function without event

    CTRLINK_RCV_TX_SIZE=16*1024,  //Should be 32K
    CTRLINK_RCV_RX_SIZE=4*1024,

    //Receiver bus (down converter 1,2,3)
    CTRLINK_RCV_TX_A    = 0x00000000,   CTRLINK_RCV_TX_A_EVENT  =0x00,
    CTRLINK_RCV_TX_B    = 0x00010000,   CTRLINK_RCV_TX_B_EVENT  =0x01,

    CTRLINK_RCV_RX_A    = 0x00020000,   CTRLINK_RCV_RX_A_EVENT  =FPGA_EVENT_INVALID,
    CTRLINK_RCV_RX_B    = 0x00028000,   CTRLINK_RCV_RX_B_EVENT  =FPGA_EVENT_INVALID,

    //Exciter bus (exciter and synth)
    CTRLINK_EXC_TX_A    = 0x10000000,   CTRLINK_EXC_TX_A_EVENT  =0x09,
    CTRLINK_EXC_TX_B    = 0x10010000,   CTRLINK_EXC_TX_B_EVENT  =0x0A,

    CTRLINK_EXC_RX_A    = 0x10020000,   CTRLINK_EXC_RX_A_EVENT  =FPGA_EVENT_INVALID,
    CTRLINK_EXC_RX_B    = 0x10028000,   CTRLINK_EXC_RX_B_EVENT  =FPGA_EVENT_INVALID,

    //Timetag generator (single buffer)
    TTAG_SZIE= 256,      //Allocated 4K

    TTAG_GEN            = 0x49000000,   TTAG_EVENT              =0x08,

    //Timer
    TIMER_SIZE= 4*1024, //this is the max size, sela size is the sizeof of the FW register struct

    TIMER_A             = 0x44A10000,   TIMER_A_EVENT           =0x02,
    TIMER_B             = 0x44A12000,   TIMER_B_EVENT           =0x03,

    //AESA
    AESA_TX_SIZE= 8*1024,
    AESA_RX_SIZE= 4*1024,

    AESA_TX_A           = 0xD0040000,   AESA_TX_A_EVENT         =0x04,
    AESA_TX_B           = 0xD0048000,   AESA_TX_B_EVENT         =0x05,

    AESA_RX_A           = 0xD0050000,   AESA_RX_A_EVENT         =0x06,
    AESA_RX_B           = 0xD0054000,   AESA_RX_B_EVENT         =0x07,

    AESA_RX_A_R         = 0xD0058000,   AESA_RX_A_R_EVENT       =AESA_RX_A_EVENT,
    AESA_RX_B_R         = 0xD005C000,   AESA_RX_B_R_EVENT       =AESA_RX_B_EVENT,

    //AD direct acquire buffer (single buffer)
    AD_ACQ_CH_SIZE=8*1024,
    AD_ACQ_CH_NUM =4, //It is 12, 4 for preliminary test with only one DC
    AD_ACQ_SIZE   =AD_ACQ_CH_SIZE*AD_ACQ_CH_NUM,

    AD_ACQ              = 0x50000000,   AD_ACQ_EVENT            =0x0B, //start acq
                                        AD_ACQ_RESET            =0x0E,

    //Signal processing:
    DETECTOR_SIZE = 8*1024,
    DETECTOR_A    =0x55000000, DETECTOR_A_EVENT = 0x0C,
    DETECTOR_B    =DETECTOR_A+0x4000, DETECTOR_B_EVENT = 0x0D,

    EXPANDER_SIZE = 0x1000,
    EXPANDER_A    =0x58200000, EXPANDER_A_EVENT = 0x0F,
    EXPANDER_B    =0x58200400, EXPANDER_B_EVENT = 0x25,
                               EXPANDER_ENABLE_EVENT = 0x22,

    PC_SIZE = 8*1024,  //WARNING: Lite version!!!
    PC_A    =0x57000000, PC_A_EVENT = 0x23,
    PC_B    =PC_A+0x020000, PC_B_EVENT = 0x24,

    DISPATCHER_SIZE = 0x100,
    DISPATCHER_A = 0x56000000, DISPATCHER_A_EVENT = 0x20,
    DISPATCHER_B = 0x56000200, DISPATCHER_B_EVENT = 0x21,

    HEADER_SIZE = 4*1024,
    HEADER_A = 0x56004000, HEADER_A_EVENT =FPGA_EVENT_INVALID,
    HEADER_B = 0x56005000, HEADER_B_EVENT =FPGA_EVENT_INVALID,

    //A scratch buffer, mapped on the FPGA DDR
    SCRATCH             = 0xA0000000

};

static inline unsigned int fpga_map_to_uint(fpga_map_t v) { return static_cast<unsigned int>(v);}

}//namespace

#endif // GRIFO_FW_ADDRESSES_H
