/* * fpgaflashconfig.h * * * author: Luca Vallongo * */ #ifndef FPGAFLASHCONFIG_H #define FPGAFLASHCONFIG_H //TEST PARAMETERS //#define NUM_BLOCKS_ERASE 2 //#define DIM_FILE_WRITE 131072 //number of flash present into system #define NUM_FLASH 10 //number of Counter repeat before reset #define MAX_COUNTER_REPEAT 999 //Software Reset Register (SRR) #define SRR_KEYCODE 0x12ABCDEF //timeout for spi comunication #define TIMEOUT_SPI 2000 #define WAIT_TIME_AFTER_WR 0 //wait after write #define WAIT_TIME_BEFORE_RD 5 //wait before read #define WAIT_TIME_AFTER_RD 0 //wait after read #define WAIT_TIME_BEFORE_NEW_RD 5 //wait before new read, in case of repeat read #define WAIT_TIME_BETWEEN_2_OP 0 //wait between two basic operation #define WAIT_TIME_BETWEEN_2_MACRO 0 //wait between two macro operation(for example, between erase and confirm) #define WAIT_TIME_INIT_OPERATION 100 //wait for reset, read flash id, set SQPI #define NUM_REPEAT_READ 3 //number of repeat to read on tftp before error on tftp #define NUM_REPEAT_WRITE 3 //number of repeat to read on tftp before error on tftp //base address for interface #define BASE_ADDRESS_IF 0x47000000 //base address for ddr memory for test #define BASE_ADDRESS_MEM 0xA0000000 //if define NO_WRITE_ERASE, the app doesn't erase and write the flash //#define NO_WRITE_ERASE //comment this line for enable write/erase flash memory // FPGA(s) #define I2C_FPGA1_ADD 0x60 #define I2C_FPGA2_ADD 0x61 #define FPGA_C_MEM_SLOT_ADD 0x44000000 // Carrier #define FPGA_C_MEM_WR_ADD 0x44000780 // Carrier #define FPGA_C_MEM_RD_ADD 0x44000800 // Carrier #define FPGA_Z_MEM_SLOT_ADD 0x500E0000 // ZYNQ #define FPGA_Z_MEM_WR_ADD 0x500E0780 // ZYNQ #define FPGA_Z_MEM_RD_ADD 0x500E0800 // ZYNQ #define FPGA_FW_PAGE_SIZE 256 // Page size for firmware download [bytes] #define FLASH_SECTOR_DIM 64 //kbytes, dimension of one sector of the flash #define FLASH_128Mbit 128 #define FLASH_256Mbit 256 #include //3 types of flash, different characteristics enum flash_type_t { flash_type_xcku040, flash_type_xcku060, flash_type_xc7a200 }; //two different flash area enum flash_firmware_area_t { flash_firmware_area_golden, //not writeable without confirm flash_firmware_area_user //usualy writeable area }; //bytes address for different flash type enum reg_moder_byteaddress_t { bytes3address =0, //3 bytes address bytes4address =1 //4 bytes address }; //QSPI port enum reg_moder_qspiport_t { primarySpiPort =0, //use primary SPI interface port secondarySpiPort =1 //use secondary SPI interface port }; class TgtMatch { public: QString appName; QString slotAddress; QString archName; QString description; QString tgtName; QString partName; QString matchStr; QString address_start_area; //hex address, start fimware area QString address_stop_area; //hex address, stop fimware area flash_firmware_area_t firmware_area; //golden/user FW flash_type_t type; //xcku040, xcku060, xc7a200 reg_moder_byteaddress_t byteaddress ; //3/4 byte address reg_moder_qspiport_t spiPort; //use primary/secondary SPI interface port QString tgtSection; //target section into config file QString ip; int port; QRegExp rexp; QTreeWidgetItem* wi; }; class TgtMatchSet { public: QList db; TgtMatch* add( const QString& aName, const QString& sName, const QString& tName, const QString& pName, const QString& namePrefix, const QString& descr, const QString& arch, const QString& _address_start_area, const QString& _address_stop_area, const flash_firmware_area_t& _firmware_area, const flash_type_t& _type, const reg_moder_byteaddress_t& _byteaddress, const reg_moder_qspiport_t& _spiPort, const QString& _ip, const int& _port, const QString & _tgtSection ); const TgtMatch* lookup(const QString& fname); const TgtMatch* lookupArch(const QString& arc); TgtMatch* lookupCSCI(const QString& fname, const QString sAddr); const TgtMatch* lookupTgtSection(QString _tgtSection); const TgtMatch* lookupAppName(const QString& fname); }; #endif // FPGAFLASHCONFIG_H