[default]
port=50069
ip="192.168.2.101"
smart=1
section=APP1
srio_base=$0x500000
fpga_base=$0x0
fpga_sector=0x010000

[TGT-0]
appName=EIF/FPGA0
description="SATA"
slotAddress=$0x13
arch=Xilinx
name=EIF/FPGA0
section=
filePrefix=FPGA-
addressStartArea

[TGT-1]
appName=EIF/FPGA1
description="?"
slotAddress=$0x73
arch=Xilinx
name=EIF/FPGA1
section=
filePrefix=FPGA-

[TGT-2]
appName=XIF1/FPGA0
description="?"
slotAddress=$0x14
arch=Xilinx
name=XIF1/FPGA0
section=
filePrefix=FPGA-

[TGT-3]
appName=XIF1/FPGA1
description="?"
slotAddress=$0x74
arch=Xilinx
name=XIF/FPGA1
section=
filePrefix=FPGA-

[TGT-4]
appName=XIF2/FPGA0
description="?"
slotAddress=$0x15
arch=Xilinx
name=XIF2/FPGA0
section=
filePrefix=FPGA-

[TGT-5]
appName=XIF2/FPGA1
description="?"
slotAddress=$0x75
arch=Xilinx
name=XIF2/FPGA1
section=
filePrefix=FPGA-

[TGT-6]
appName=DFE/FPGA0
description="Core FPGA"
slotAddress=$0x16
arch=Xilinx
name=DFE/CoreFPGA
section=
filePrefix=FPGA-DFE

[TGT-7]
appName=DFE/FPGA1
description="spare"
slotAddress=$0x76
arch=Xilinx
name=DFE/FPGA1
section=
filePrefix=FPGA-