[default]
port=50069
ip="192.168.2.102"
smart=1
section=APP1
srio_base=$0x500000
fpga_base=$0x0
fpga_sector=0x010000
defTarget=AESA_RFIF


[MODEL-0]
idModel=0
model=xcku040
description=128Mbit xcku040
type=0
3_4Byte=0
numSector=256
goldenAddressStartArea=0x00000000
goldenAddressStopArea=0x007FFFFF
userAddressStartArea=0x00800000
userAddresStopArea=0x00FFFFFF

[MODEL-1]
idModel=1
model=xcku060
description=128Mbit xcku060
type=1
3_4Byte=1
numSector=512
goldenAddressStartArea=0x00000000
goldenAddressStopArea=0x00FFFFFF
userAddressStartArea=0x01000000
userAddresStopArea=0x01FFFFFF

[MODEL-2]
idModel=2
model=rfif
description=256Mbit
type=1
3_4Byte=1
numSector=512
goldenAddressStartArea=0x00000000
goldenAddressStopArea=0x003FFFFF
userAddressStartArea=0x00400000
userAddresStopArea=0x007FFFFF
testAddress=0x01F00000


[TGT-0]
idTgt=EIF_FPGA1
description=EIF FPGA1 0x13
slotAddress=0x13
arch=Xilinx
name=EIF_FPGA1
filePrefix=EIF_FPGA1
idModel=0

[TGT-1]
idTgt=EIF_FPGA2
description=EIF FPGA2 0x73
slotAddress=0x73
arch=Xilinx
name=EIF_FPGA2
filePrefix=EIF_FPGA2
idModel=0

[TGT-2]
idTgt=XIF1_FPGA1
description=XIF1/FPGA1 0x14
slotAddress=0x14
arch=Xilinx
name=XIF1_FPGA1
filePrefix=XIF1_FPGA1
idModel=0

[TGT-3]
idTgt=XIF1_FPGA2
description=XIF1/FPGA2 0x74
slotAddress=0x74
arch=Xilinx
name=XIF1_FPGA2
filePrefix=XIF1_FPGA2
idModel=0

[TGT-4]
idTgt=XIF2_FPGA1
description=XIF2/FPGA1 0x15
slotAddress=0x15
arch=Xilinx
name=XIF2_FPGA1
filePrefix=XIF2_FPGA1
idModel=0

[TGT-5]
idTgt=XIF2_FPGA2
description=XIF2/FPGA2 0x75
slotAddress=0x75
arch=Xilinx
name=XIF2_FPGA2
filePrefix=XIF2_FPGA2
idModel=0

[TGT-6]
idTgt=DFE_FPGA1
description=DFE/FPGA1 0x16
slotAddress=0x16
arch=Xilinx
name=DFE_FPGA1
filePrefix=DFE_FPGA1
idModel=1

[TGT-7]
idTgt=DFE_FPGA2
description=DFE/FPGA2 0x76
slotAddress=0x76
arch=Xilinx
name=DFE_FPGA2
filePrefix=DFE_FPGA2
idModel=0

[TGT-8]
idTgt=AESA_RFIF
description=AESA/RFIF 0x16
slotAddress=0x16
arch=RFIF
name=AESA_RFIF
filePrefix=AESA_RFIF
idModel=2