[default]
port=50069
ip="192.168.2.102"
smart=1
section=APP1
srio_base=$0x500000
fpga_base=$0x0
fpga_sector=0x010000
defTarget=EIF/FPGA1_U_P

[TGT-0]
appName=EIF/FPGA1_G_P
description="Golden"
slotAddress=$0x73
arch=Xilinx
name=EIF/FPGA1_Golden_S
section=
filePrefix=FPGA-
addressStartArea=0x00000000
addressStopArea=0x007FFFFF
area=0
type=0
3_4Byte=0
spiPort=0
numSector=128

[TGT-1]
appName=EIF/FPGA1_G_S
description="Golden"
slotAddress=$0x73
arch=Xilinx
name=EIF/FPGA1_Golden_S
section=
filePrefix=FPGA-
addressStartArea=0x00000000
addressStopArea=0x007FFFFF
area=0
type=0
3_4Byte=0
spiPort=1
numSector=128

[TGT-2]
appName=EIF/FPGA1_U_P
description="User"
slotAddress=$0x73
arch=Xilinx
name=EIF/FPGA1_User_P
section=
filePrefix=FPGA-
addressStartArea=0x00800000
addressStopArea=0x00FFFFFF
area=1
type=0
3_4Byte=0
spiPort=0
numSector=128

[TGT-3]
appName=EIF/FPGA1_U_S
description="User"
slotAddress=$0x73
arch=Xilinx
name=EIF/FPGA1_User_S
section=
filePrefix=FPGA-
addressStartArea=0x00800000
addressStopArea=0x00FFFFFF
area=1
type=0
3_4Byte=0
spiPort=1
numSector=128