[default]
port = 50069
ip = "192.168.2.102"
smart = 1
section = APP1
srio_base = $0x500000
fpga_base = $0x0
fpga_sector = 0x010000
deftarget = AESA_RFIF

[MODEL-0]
idmodel = 0
model = xcku040
description = 128Mbit xcku040
type = 0
3_4byte = 0
numsector = 256
goldenaddressstartarea = 0x00000000
goldenaddressstoparea = 0x007FFFFF
useraddressstartarea = 0x00800000
useraddresstoparea = 0x00FFFFFF

[MODEL-1]
idmodel = 1
model = xcku060
description = 128Mbit xcku060
type = 1
3_4byte = 1
numsector = 512
goldenaddressstartarea = 0x00000000
goldenaddressstoparea = 0x00FFFFFF
useraddressstartarea = 0x01000000
useraddresstoparea = 0x01FFFFFF

[MODEL-2]
idmodel = 2
model = rfif
description = 256Mbit
type = 1
3_4byte = 1
numsector = 512
goldenaddressstartarea = 0x00000000
goldenaddressstoparea = 0x003FFFFF
useraddressstartarea = 0x00400000
useraddresstoparea = 0x007FFFFF
testaddress = 0x01F00000

[TGT-0]
idtgt = AESA_RFIF
description = AESA/RFIF 0x16
slotaddress = 0x16
arch = RFIF
name = AESA_RFIF
fileprefix = AESA_RFIF
idmodel = 2

[TGT-1]
idtgt = DFE_FPGA1
description = DFE/FPGA1 0x16
slotaddress = 0x16
arch = Xilinx
name = DFE_FPGA1
fileprefix = DFE_FPGA1
idmodel = 1

[TGT-2]
idtgt = DFE_FPGA2
description = DFE/FPGA2 0x76
slotaddress = 0x76
arch = Xilinx
name = DFE_FPGA2
fileprefix = DFE_FPGA2
idmodel = 0

[TGT-3]
idtgt = EIF_FPGA1
description = EIF FPGA1 0x13
slotaddress = 0x13
arch = Xilinx
name = EIF_FPGA1
fileprefix = EIF_FPGA1
idmodel = 0

[TGT-4]
idtgt = EIF_FPGA2
description = EIF FPGA2 0x73
slotaddress = 0x73
arch = Xilinx
name = EIF_FPGA2
fileprefix = EIF_FPGA2
idmodel = 0

[TGT-5]
idtgt = XIF1_FPGA1
description = XIF1/FPGA1 0x14
slotaddress = 0x14
arch = Xilinx
name = XIF1_FPGA1
fileprefix = XIF1_FPGA1
idmodel = 0

[TGT-6]
idtgt = XIF1_FPGA2
description = XIF1/FPGA2 0x74
slotaddress = 0x74
arch = Xilinx
name = XIF1_FPGA2
fileprefix = XIF1_FPGA2
idmodel = 0

[TGT-7]
idtgt = XIF2_FPGA1
description = XIF2/FPGA1 0x15
slotaddress = 0x15
arch = Xilinx
name = XIF2_FPGA1
fileprefix = XIF2_FPGA1
idmodel = 0

[TGT-8]
idtgt = XIF2_FPGA2
description = XIF2/FPGA2 0x75
slotaddress = 0x75
arch = Xilinx
name = XIF2_FPGA2
fileprefix = XIF2_FPGA2
idmodel = 0