129 lines
2.1 KiB
INI
129 lines
2.1 KiB
INI
[default]
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port = 50069
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ip = "192.168.2.102"
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smart = 1
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section = APP1
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srio_base = $0x500000
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fpga_base = $0x0
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fpga_sector = 0x010000
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deftarget = AESA_RFIF
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[MODEL-0]
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idmodel = 0
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model = xcku040
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description = 128Mbit xcku040
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type = 0
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3_4byte = 0
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numsector = 256
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goldenaddressstartarea = 0x00000000
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goldenaddressstoparea = 0x007FFFFF
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useraddressstartarea = 0x00800000
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useraddresstoparea = 0x00FFFFFF
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[MODEL-1]
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idmodel = 1
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model = xcku060
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description = 128Mbit xcku060
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type = 1
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3_4byte = 1
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numsector = 512
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goldenaddressstartarea = 0x00000000
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goldenaddressstoparea = 0x00FFFFFF
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useraddressstartarea = 0x01000000
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useraddresstoparea = 0x01FFFFFF
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[MODEL-2]
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idmodel = 2
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model = rfif
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description = 256Mbit
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type = 1
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3_4byte = 1
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numsector = 512
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goldenaddressstartarea = 0x00000000
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goldenaddressstoparea = 0x003FFFFF
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useraddressstartarea = 0x00400000
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useraddresstoparea = 0x007FFFFF
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testaddress = 0x01F00000
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[TGT-0]
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idtgt = AESA_RFIF
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description = AESA/RFIF 0x16
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slotaddress = 0x16
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arch = RFIF
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name = AESA_RFIF
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fileprefix = AESA_RFIF
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idmodel = 2
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[TGT-1]
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idtgt = DFE_FPGA1
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description = DFE/FPGA1 0x16
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slotaddress = 0x16
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arch = Xilinx
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name = DFE_FPGA1
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fileprefix = DFE_FPGA1
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idmodel = 1
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[TGT-2]
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idtgt = DFE_FPGA2
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description = DFE/FPGA2 0x76
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slotaddress = 0x76
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arch = Xilinx
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name = DFE_FPGA2
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fileprefix = DFE_FPGA2
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idmodel = 0
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[TGT-3]
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idtgt = EIF_FPGA1
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description = EIF FPGA1 0x13
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slotaddress = 0x13
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arch = Xilinx
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name = EIF_FPGA1
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fileprefix = EIF_FPGA1
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idmodel = 0
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[TGT-4]
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idtgt = EIF_FPGA2
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description = EIF FPGA2 0x73
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slotaddress = 0x73
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arch = Xilinx
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name = EIF_FPGA2
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fileprefix = EIF_FPGA2
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idmodel = 0
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[TGT-5]
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idtgt = XIF1_FPGA1
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description = XIF1/FPGA1 0x14
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slotaddress = 0x14
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arch = Xilinx
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name = XIF1_FPGA1
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fileprefix = XIF1_FPGA1
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idmodel = 0
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[TGT-6]
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idtgt = XIF1_FPGA2
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description = XIF1/FPGA2 0x74
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slotaddress = 0x74
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arch = Xilinx
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name = XIF1_FPGA2
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fileprefix = XIF1_FPGA2
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idmodel = 0
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[TGT-7]
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idtgt = XIF2_FPGA1
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description = XIF2/FPGA1 0x15
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slotaddress = 0x15
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arch = Xilinx
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name = XIF2_FPGA1
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fileprefix = XIF2_FPGA1
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idmodel = 0
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[TGT-8]
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idtgt = XIF2_FPGA2
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description = XIF2/FPGA2 0x75
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slotaddress = 0x75
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arch = Xilinx
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name = XIF2_FPGA2
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fileprefix = XIF2_FPGA2
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idmodel = 0
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