142 lines
4.8 KiB
C
142 lines
4.8 KiB
C
#ifndef FPGAFLASHENGINE_H
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#define FPGAFLASHENGINE_H
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#include <stdint.h>
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#include <exception>
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#include "fpgaflashconfig.h"
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#include "mydebug.h"
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//Profilo contentente i dati della FPGA da utilizzare
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class FpgaFlashProfile
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{
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public:
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unsigned long SectorSize_KBytes;
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unsigned long BaseAddress;
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unsigned long BaseOffset;
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reg_moder_qspiport_t spiport;
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reg_moder_byteaddress_t byteddress;
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unsigned long address_start_area; //hex address, start fimware area
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unsigned long address_stop_area; //hex address, stop fimware area
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QString ip;
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QString port;
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QString slotAddress;
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QString FileToSend; //complete path of file to send
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int dimMbit; //128Mbit for xcku040
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//256Mbit for xcku060, xc7a200
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bool writeRamp; //instead file, write ramp into flash
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bool verifySector; //verify single sector
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bool verifyFinal; //verify final write
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void reset()
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{
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SectorSize_KBytes = 0;
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BaseAddress = 0;
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BaseOffset = 0;
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spiport = primarySpiPort;
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byteddress = bytes3address;
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address_start_area = 0;
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address_stop_area = 0;
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ip = QString("");
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port = QString("");
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slotAddress = QString("");
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FileToSend = QString("");
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dimMbit = 0;
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writeRamp = false;
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verifyFinal = false;
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verifySector = false;
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}
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};
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enum spisr_bit_t
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{
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rx_fifo_valid = 0x1, //bit 0, This bit flags that data present into SPIRR is valid
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rx_fifo_overrun = 0x2, //bit 1, This bit flags that an overrun error occurred during data reception into the RX FIFO.
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tx_fifo_almost_full = 0x10, //bit 4, This bit flags that an almost full condition occurred loading the TX FIFO. In particular this condition is activated when the number of bytes into the FIFO differs from respect the FIFO size.
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tx_fifo_overrun = 0x20, //bit 5, This bit flags that an overrun error occurred loading data into the TX FIFO.
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tx_fifo_underrun = 0x40, //bit 6, This bit flags that an underrun error occurred into the TX FIFO during data transmission.
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spi_core_error = 0x400, //bit 10, The SPI Core error flags an error condition during transaction. This condition can be activated: - when an overrun or underrun is detected (on both "TX FIFO" or "RX FIFO") - when the required command is not implemented
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spi_core_ack = 0x800, //bit 11, This bit is activated when a previously required transaction required with the "SPI request" on the SPICR register has been accepted
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spi_core_busy = 0x1000 //bit 12, This bit is activated when the core is executing the current transaction after that it has been run with the "SPI start" bit on the SPICR register.
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};
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bool decodeSPISR(unsigned int _spisr, spisr_bit_t _bit);
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unsigned int encodeSPISR(unsigned int _spisr, spisr_bit_t _bit);
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class FpgaFlashInterface
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{
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public:
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enum step_t
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{
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s_init=0,
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s_reset,
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s_status,
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s_read_id,
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s_erase,
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s_write,
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s_end
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};
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virtual bool rtgWrite(uint32_t address, const void* data, unsigned int len=256)=0;
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virtual bool rtgRead(uint32_t address, void* data, unsigned int len=256)=0;
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//virtual bool rtgErase(uint32_t address, void* data, unsigned int len=256)=0;
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virtual bool rtgReadDirect(uint32_t address, void* data, unsigned int len=256)=0;
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virtual bool rtgWaitEvent(unsigned int timeout_ms=5000)=0;
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virtual void notify(step_t sts, int progress, const char* msg, ...);
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virtual void log(type_log_t level, const char* msg, ...);//level<0: error, ==0: info, >0: success
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virtual unsigned long timeNowMs();
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virtual ~FpgaFlashInterface();
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virtual void setLogLevel(log_level_t _level);
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virtual log_level_t getLogLevel();
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log_level_t log_level;
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};
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class FpgaFlashEngine
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{
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public:
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FpgaFlashEngine();
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void setProfile(const FpgaFlashProfile& profile);
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void setInterface(FpgaFlashInterface* flashInterface);
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bool fpgaErase(const void* data, unsigned int size);
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bool fpgaProgram(const void* data, unsigned int size);
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bool fpgaReset();
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bool fpgaTerminate();
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bool readFlashID();
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bool readStatusSPI();
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bool simulateWrite(uint32_t address, const void* data, unsigned int len);
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bool simulateRead(uint32_t address, void *data, unsigned int len);
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bool simulateErase(uint32_t address, void *data, unsigned int len);
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bool simulateReset();
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bool simulateReadStatusSPI();
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bool simulateTerminate();
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unsigned int simulateReadFlashID();
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bool getEnableMsgBlk();
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};
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#endif // FPGAFLASHENGINE_H
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