305 lines
10 KiB
C++
305 lines
10 KiB
C++
#ifndef FPGARFIFFLASHOPERATION_H
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#define FPGARFIFFLASHOPERATION_H
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#include <string.h>
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#include <map>
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#include "fpgarfifflashengine.h"
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#include "fpgaflashconfig.h"
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#include "grifo_aesa_fw_if.h"
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#define FLASH_ID_SIZE 4
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#define FLASH_ID_NUMBER_OF_BYTES 20
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// 5.5 Register Space, AXI_QSPIFlash_IF_PG Rev. A, pag 16
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#define R32_(x_) ((x_)/4)
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/*enum reg_offset_t
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{
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//RW -> read write
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//RO -> read only
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r_base =R32_(0),
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r_moder =R32_(0x02C), //RW Mode Register
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r_cmdr =R32_(0x030), //RW Command Register
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r_addrr =R32_(0x034), //RW Address Register
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r_nbr =R32_(0x038), //RW Number of bytes Register
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r_srr =R32_(0x040), //RW Software Reset Register
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r_spicr =R32_(0x060), //RW SPI Control Register
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r_spidtr =R32_(0x400), //RW SPI Transmit FIFO Register
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r_spi_status_base =R32_(0x800), //RO SPI Status base
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r_spisr =R32_(0x864), //RO SPI Status Register
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r_txfifoocy =R32_(0x874), //RO TX FIFO Occupancy Register
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r_rxfifoocy =R32_(0x878), //RO RX FIFO Occupancy Register
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r_spirr =R32_(0xC00), //RO SPI Receive FIFO Register
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r_gier =R32_(0x01C), //RW Global Interrupt Enable Register
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r_icsr =R32_(0x020), //RW Interrupt Clear Status Register
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r_ier =R32_(0x028), //RW Interrupt Enable Register
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r_isr =R32_(0x820), //RO Interrupt Status Register
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adr_fifo=r_base+r_spidtr
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};*/
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enum type_cmd_t
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{
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cmd_nc, //cmd without read and write
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cmd_read, //cmd with read
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//cmd_read_flashID, //cmd with read
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cmd_write, //cmd with write
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};
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//## type common_enums_t
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enum common_enums_t
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{
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NUM_MAX_RESPONSES = 6,
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RESPONSE_TABLE_SIZE = 8, // number of substates where AC responses are expected
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AESA_READ_FW_STATUS_TIMEOUT_US = 30000, // microseconds
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AESA_RFIF_READ_FW_STATUS_TIMEOUT_US = 2000, // microseconds
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AESA_READ_STATUS_TIMEOUT_US = 20000, // microseconds
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RFIF_READ_STATUS_TIMEOUT_US = 2000, // microseconds
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RFIF_READ_BIT_STATUS_TIMEOUT_US = 3000000, // microseconds (value is TBD)
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AESA_PLANK_TRC_INIT_TIMEOUT_US = 40000, // microseconds
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RFIF_MODE_TIMEOUT_US = 100, // microseconds
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PLANK_VTX_CTRL_TIMEOUT_US = 150000, // microseconds
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CALC_BEAM_POS_TIMEOUT_US = 100, // microseconds
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AESA_DOWNLOAD_MAP_TIMEOUT_US = 20000, // microseconds
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GET_VERSION_TIMEOUT_MS = 50, // milliseconds (to be tuned)
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READ_STATUS_TIMEOUT_MS = 40, // milliseconds (to be tuned)
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RFIF_STATUS_TIMEOUT_MS = 4000, // milliseconds (to be tuned)
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TRC_INIT_TIMEOUT_MS = 100, // milliseconds (to be tuned)
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RFIF_RADIATE_TIMEOUT_MS = 150, // milliseconds (to be tuned)
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TVX_BMC_ENABLE_TIMEOUT_MS = 2000, // milliseconds (to be tuned)
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BEAM_CALCULATE_TIMEOUT_MS = 20, // milliseconds (to be tuned)
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DOWNLOAD_MAP_TIMEOUT_MS = 50, // milliseconds (to be tuned)
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GET_RESPONSE_TIMEOUT_MS = 10000, // milliseconds (to be tuned)
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OPERATIVE_TO_STANDBY_TIMEOUT_MS = 5000, // milliseconds (to be tuned)
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STANDBY_TO_OPERATIVE_TIMEOUT_MS = 5000, // milliseconds (to be tuned)
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MAX_NUMBER_PRT_IN_A_BATCH = 128, // maximum number of prt par batch
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CTI_READ_STATUS_TIMEOUT_MS = 2000 // milliseconds (to be tuned)
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};
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//## type ACErrorEnum
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enum ACErrorEnum
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{
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eACOk = 0,
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eACSrioTimeOut = 1,
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eACFpgaTimeOut = 2,
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eACFpgaCRCErr = 4,
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eACFpgaLenErr = 8,
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eACUnknownErr = 16,
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eACTotalCommFail = 32,
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eACCtiLinkErr = (1<<8),
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eACCtiCRCErr = (1<<9),
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eACCtiCodingErr = (1<<10),
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eACCtiBeamErr = (1<<11),
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eACCtiDutyPulseErr = (1<<12),
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eACCtiUnknownErr = (1<<16)
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};
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enum emu_common_enums_t
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{
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MAX_PLANKS = 64,
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MAX_TRC_PER_PLANKS = 32,
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NUM_PLANK_PCBS = 32,
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NUM_TRCS = 20
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};
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//## type trc_map_status_t
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enum emu_trc_map_status_t
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{
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NO_MAPPING_FAILURE = 0,
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LINK_FAILURE = 1,
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MAP_PASS_1_BIT_FAILURE = 2,
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MAP_PASS_2_BIT_FAILURE = 3
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};
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struct EmuAesaStatusTrcResponse
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{
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enum { trc_per_byte=4, trc_per_plank=20};
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uint8_t trcx_raw[trc_per_plank/trc_per_byte];
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uint8_t extractByte(unsigned int trcn) const
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{
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unsigned int bindex=trcn/4;
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return trcx_raw[bindex];
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}
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uint8_t extractTrc(unsigned int trcn) const
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{
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unsigned int bindex=trcn/4;
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uint8_t sts=trcx_raw[bindex];
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unsigned int shift=trcn & (trc_per_byte-1);
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sts=sts>>(shift*2);
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sts=sts & 0x3;
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return sts;
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}
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bool fail(unsigned int trcn) const
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{
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return extractTrc(trcn)!=0;
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}
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bool commFault(unsigned int trcn) const
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{
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return extractTrc(trcn) & 1;
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}
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bool otherFault(unsigned int trcn) const
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{
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return extractTrc(trcn) & 2;
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}
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};
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struct AesaStatusResponse
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{
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uint8_t first_plank;
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uint8_t last_plank;
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aesa::cti_status_t cti_sts;
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aesa::cti_extended_status_t cti_ext_sts;
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aesa::cti_eti_readback_status_t cti_eti;
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struct plank_trcx_sts_t
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{
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aesa::plank_status_t plank_sts;
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EmuAesaStatusTrcResponse trc_sts;
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} plank[NUM_PLANK_PCBS];
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};
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class FlashOperationRFIF
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{
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public:
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FpgaFlashProfile profile;
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FpgaFlashInterface* fif;
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FpgaFlashEngineRFIF* engine;
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bool enabledMsgBlk; //enable message block
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bool getEnableMsgBlk();
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void setEnableMsgBlk(bool _enable);
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uint32_t FLASH_ID[FLASH_ID_SIZE];
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//NUOVE FUNZIONI
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bool sendCommandToAesa(unsigned int cmd);
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bool sendAESAGetVersionCmd();
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bool sendCTIGetStatusCmd();
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bool sendRFIFGetVersionCmd();
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bool decodeAesaResponse(unsigned int idx);
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bool sendCommand(unsigned int cmd);
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bool getRFIFStatusCmd();
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uint8_t message_count;
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bool processRfifStatus_OLD(const aesa::rfif_status_t sts,
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unsigned int *bit7_CFGM_BUSY,
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unsigned int *bit6_CFGM_TIMEOUT_FAIL);
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bool isConfirmed();
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void SaveBlobToFile(std::string const _file_name = "");
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void SaveBufferToFile(std::string const _file_name,
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const void* data,
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unsigned int size);
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bool isResponseOk(const void *src,
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unsigned int max_size,
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unsigned int *count);
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bool getParameters(unsigned int cmd,
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unsigned int *rfif_cmd,
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unsigned int *rfif_cmd_size,
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unsigned int *rfif_response,
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unsigned int *rfif_response_size,
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QString *msg);
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void processAesaFwStatus(const aesa::aesa_firmware_status_t* sts);
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void processRfifFwStatus(const aesa::rfif_fw_status_t* sts);
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bool processRfifStatus(const aesa::rfif_status_t* sts);
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void processCTIStatus(const aesa::cti_status_t* sts);
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void processRfifBitStatus(const aesa::rfif_bit_status_t* sts);
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void processAesaStatus(const AesaStatusResponse* sts);
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void processRfifCFGMemStatus(uint8_t *data, unsigned int len_payload);
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bool eraseRFIFCFGMem(unsigned long sector_address, unsigned int sector_size);
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bool readRFIFCFGMem(unsigned long sector_address, unsigned int sector_size);
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bool writeRFIFCFGMem(unsigned long sector_address, unsigned int sector_size, const char* data);
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bool writeRampRFIFCFGMem(unsigned long sector_address, unsigned int sector_size);
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// VECCHIE FUNZIONI
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// INITIALIZE operations, 2.4.1.1 Inizializzazione
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// Inizialize mode register, set engine
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void init(FpgaFlashEngineRFIF* engine_);
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// Initialize connection without set engine
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void init();
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// Read FLASH ID
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bool readFlashID();
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//2.4.1.4 Read (singolo data chunk di 256 byte)
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void readDataChunk(int size,void* data);
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bool program(const void* data, unsigned int size);
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//Questo comando legge lo stato del registro di stato della Flash al fine di aspettare
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//l'avvenuta scrittura del pacchetto dati tramite il bit di "Write In Progress"
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bool getWriteInProgress();
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// Erase from profile.BaseOffset for size
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bool eraseForSize(unsigned int size);
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//terminazione
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bool terminateDigitalCtrl();
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bool terminateOtherFPGA();
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private:
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//ERASE OPERATION, erase sector
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//bool eraseSector(unsigned long sector_address, unsigned int sector_size);
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//void printDebugFlashConfig();
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bool fpgaWrite(uint32_t address, const void* data, unsigned int len=DIM_DATA_BUFFER, const char* mess="", unsigned int doorbell=0);
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bool fpgaRead(uint32_t address, void* data, unsigned int len=DIM_DATA_BUFFER, const char* mess="", unsigned int doorbell=0);
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//return stirng description for cmd
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//char* retCommand(unsigned int cmd);
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unsigned int counterRepeat;
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void incrCounterRepeat();
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bool readStatusFlagRegister();
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bool requestInfoFpga();
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bool IsFPGAflashable();
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//function to test if fpga is flashable
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bool eraseTest();
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bool writeTest();
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bool readTest();
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bool IsRFIFStatusOK();
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bool EraseSingleBlock(unsigned int address);
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bool EraseAllRFIFFpga(unsigned int address, unsigned int size);
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bool writeAllRFIFFpga(unsigned int start_address, const void* data, unsigned int size);
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bool readAllRFIFFpga(unsigned int start_address, const void* data, unsigned int size);
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};
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#endif // FPGARFIFFLASHOPERATION_H
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