//!;;Rpy::+
//!;;Rpy::ModelElement: idd_comm::idd_nodeid
//!;;Rpy::
//!;;Rpy::Component: IDDComponent 
//!;;Rpy::Configuration: IDDConfig
//!;;Rpy::Project: IDD
//!;;Rpy::
//!;;Rpy::FilePath: idd_nodeid.h
//!;;Rpy::Tag: $Tag
//!;;Rpy::
//!;;Rpy::Copyright: Leonardocompany - COMPANY RESTRICTED
//!;;Rpy::
//!;;Rpy::Generated by Rhapsody: 7.5.3 
//!;;Rpy::-


#ifndef idd_nodeid_H
#define idd_nodeid_H

//## auto_generated
#include "idd_comm.h"
namespace idd_comm
{
    //## package idd_comm::idd_nodeid
    
    
    //## type nodeid_t
    enum nodeid_t
    {
        NONE = 0,
        CMP = 1,
        CDP = 2,
        DSP0 = 3,
        DSP1 = 4,
        DSP2 = 5,
        DSP3 = 6,
        DSP4 = 7,
        CORE_FPGA = 8, // This mainly incarnate the Timer
        SIM_TIMER_EXT = 100
    };
}

#endif
//;;Rpy:: end


