//!;;Rpy::+ //!;;Rpy::ModelElement: iddbite //!;;Rpy:: //!;;Rpy::Component: IDDComponent //!;;Rpy::Configuration: IDDConfig //!;;Rpy::Project: IDD //!;;Rpy:: //!;;Rpy::FilePath: iddbite.h //!;;Rpy::Tag: $Tag //!;;Rpy:: //!;;Rpy::Copyright: Leonardocompany - COMPANY RESTRICTED //!;;Rpy:: //!;;Rpy::Generated by Rhapsody: 7.5.3 //!;;Rpy::- #ifndef iddbite_H #define iddbite_H //## dependency aesa_report #include "aesa_report.h" //## dependency ctrlink_report #include "ctrlink_report.h" //## dependency iddtypes #include "iddtypes.h" //## dependency sensor_report #include "sensor_report.h" //## dependency srio_report #include "srio_report.h" //## package iddbite //#[ type dfe_bite_report_t struct dfe_bite_report_t { srio_report_t srio_report; srio_report_t srio_report_latched; ctrlink_report_t ctrlink_report; ctrlink_report_t ctrlink_report_latched; sensor_report_t fpga1; sensor_report_t fpga1_latched; sensor_report_t fpga2; sensor_report_t fpga2_latched; sensor_report_t zynq; sensor_report_t zynq_latched; }; //#] //#[ type xif_bite_report_t struct xif_bite_report_t { srio_report_t srio_report; srio_report_t srio_report_latched; sensor_report_t fpga1; sensor_report_t fpga1_latched; sensor_report_t fpga2; sensor_report_t fpga2_latched; sensor_report_t dsp1; sensor_report_t dsp1_latched; sensor_report_t dsp2; sensor_report_t dsp2_latched; }; //#] //#[ type eif_bite_report_t struct eif_bite_report_t { srio_report_t srio_report; srio_report_t srio_report_latched; sensor_report_t fpga1; sensor_report_t fpga1_latched; sensor_report_t fpga2; sensor_report_t fpga2_latched; sensor_report_t zynq; sensor_report_t zynq_latched; sensor_report_t dsp; sensor_report_t dsp_latched; }; //#] //#[ type dwc_bite_report_t struct dwc_bite_report_t { sensor_report_t fpga; sensor_report_t fpga_latched; unsigned int spare[4]; }; //#] //#[ type synth_bite_report_t struct synth_bite_report_t { sensor_report_t fpga; sensor_report_t fpga_latched; unsigned int spare[4]; }; //#] //#[ type exciter_bite_report_t struct exciter_bite_report_t { sensor_report_t fpga; sensor_report_t fpga_latched; unsigned int spare[4]; }; //#] //#[ type cdp_bite_phase_t enum cdp_bite_phase_t CPP_ENUM_BASE(int) { cdp_ph_null=0, cdp_ph1, //SR_RDR_LRU-3897 - PBIT Phase 1 information - requirement ot be fixed - ph1 is implicit in SW running and uC I/F up cdp_ph2, //Buses: SRIO, Ctrl link, AESA, allocated to SR_RDR_LRU-3908 - PBIT - Phase3, but required in PH2 as prerequisite to PH3 cdp_ph3, //SR_RDR_LRU-3908 - PBIT - Phase3 - STC, NAGC, ADC/DAC performance (??) cdp_ph_calibration, cdp_ph_4, //minimum radiation test (fast and simple bouncing test) cdp_ph_5 //full radiaiton test (full bouncing test) }; //#] //#[ type cdp_bite_report_t struct cdp_bite_report_t { eif_bite_report_t eif; xif_bite_report_t xif[2]; dfe_bite_report_t dfe; dwc_bite_report_t dwc[3]; synth_bite_report_t synth; exciter_bite_report_t exciter; aesa_synthetic_report_t aesa_synthetic; //aesa_bite_report_t aesa; }; //#] //#[ type cdp_bite_status_t struct cdp_bite_status_t { enum rf_fails_codes_t { rf_stc_fail=(1<<0), rf_nagc_fail=(1<<1) }; cdp_bite_phase_t phase; unsigned int validity; unsigned int rf_fails; unsigned int cal_fails; unsigned int ch_fails; unsigned int rf_group_fails; unsigned int spare[4]; }; //#] //#[ type cdp_rf_bite_report_t struct cdp_rf_bite_report_t { unsigned int stc_valid; unsigned int stc_fail[5][3]; //4 acq ch x 3 rf ch + 1 ac channel where to merge all the other fails unsigned int nagc_valid; unsigned int nagc_report[4]; unsigned int spare[7]; }; //#] //#[ type cdp_cal_bite_report_t struct cdp_cal_bite_report_t { unsigned int valid; unsigned cal_fail[16]; unsigned int spare[8]; }; //#] //#[ type cdp_version_info_t struct cdp_version_info_t { unsigned int valid; char ver[8]; char fpga[2][8]; }; //#] //#[ type cdp_bite_graph_info_t struct cdp_bite_graph_info_t { unsigned int valid; uint8_t graph[3][128]; }; //#] #endif //;;Rpy:: end