201 lines
4.1 KiB
C
201 lines
4.1 KiB
C
//!;;Rpy::+
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//!;;Rpy::ModelElement: iddbite
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//!;;Rpy::
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//!;;Rpy::Component: IDDComponent
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//!;;Rpy::Configuration: IDDConfig
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//!;;Rpy::Project: IDD
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//!;;Rpy::
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//!;;Rpy::FilePath: iddbite.h
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//!;;Rpy::Tag: $Tag
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//!;;Rpy::
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//!;;Rpy::Copyright: Leonardocompany - COMPANY RESTRICTED
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//!;;Rpy::
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//!;;Rpy::Generated by Rhapsody: 7.5.3
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//!;;Rpy::-
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#ifndef iddbite_H
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#define iddbite_H
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//## dependency aesa_report
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#include "aesa_report.h"
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//## dependency ctrlink_report
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#include "ctrlink_report.h"
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//## dependency iddtypes
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#include "iddtypes.h"
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//## dependency sensor_report
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#include "sensor_report.h"
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//## dependency srio_report
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#include "srio_report.h"
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//## package iddbite
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//#[ type dfe_bite_report_t
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struct dfe_bite_report_t
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{
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srio_report_t srio_report;
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srio_report_t srio_report_latched;
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ctrlink_report_t ctrlink_report;
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ctrlink_report_t ctrlink_report_latched;
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sensor_report_t fpga1;
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sensor_report_t fpga1_latched;
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sensor_report_t fpga2;
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sensor_report_t fpga2_latched;
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sensor_report_t zynq;
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sensor_report_t zynq_latched;
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};
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//#]
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//#[ type xif_bite_report_t
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struct xif_bite_report_t
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{
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srio_report_t srio_report;
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srio_report_t srio_report_latched;
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sensor_report_t fpga1;
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sensor_report_t fpga1_latched;
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sensor_report_t fpga2;
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sensor_report_t fpga2_latched;
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sensor_report_t dsp1;
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sensor_report_t dsp1_latched;
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sensor_report_t dsp2;
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sensor_report_t dsp2_latched;
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};
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//#]
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//#[ type eif_bite_report_t
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struct eif_bite_report_t
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{
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srio_report_t srio_report;
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srio_report_t srio_report_latched;
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sensor_report_t fpga1;
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sensor_report_t fpga1_latched;
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sensor_report_t fpga2;
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sensor_report_t fpga2_latched;
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sensor_report_t zynq;
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sensor_report_t zynq_latched;
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sensor_report_t dsp;
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sensor_report_t dsp_latched;
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};
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//#]
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//#[ type dwc_bite_report_t
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struct dwc_bite_report_t
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{
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sensor_report_t fpga;
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sensor_report_t fpga_latched;
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unsigned int spare[4];
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};
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//#]
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//#[ type synth_bite_report_t
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struct synth_bite_report_t
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{
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sensor_report_t fpga;
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sensor_report_t fpga_latched;
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unsigned int spare[4];
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};
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//#]
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//#[ type exciter_bite_report_t
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struct exciter_bite_report_t
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{
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sensor_report_t fpga;
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sensor_report_t fpga_latched;
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unsigned int spare[4];
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};
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//#]
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//#[ type cdp_bite_phase_t
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enum cdp_bite_phase_t CPP_ENUM_BASE(int)
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{
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cdp_ph_null=0,
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cdp_ph1, //SR_RDR_LRU-3897 - PBIT Phase 1 information - requirement ot be fixed - ph1 is implicit in SW running and uC I/F up
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cdp_ph2, //Buses: SRIO, Ctrl link, AESA, allocated to SR_RDR_LRU-3908 - PBIT - Phase3, but required in PH2 as prerequisite to PH3
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cdp_ph3, //SR_RDR_LRU-3908 - PBIT - Phase3 - STC, NAGC, ADC/DAC performance (??)
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cdp_ph_calibration,
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cdp_ph_4, //minimum radiation test (fast and simple bouncing test)
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cdp_ph_5 //full radiaiton test (full bouncing test)
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};
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//#]
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//#[ type cdp_bite_report_t
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struct cdp_bite_report_t
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{
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eif_bite_report_t eif;
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xif_bite_report_t xif[2];
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dfe_bite_report_t dfe;
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dwc_bite_report_t dwc[3];
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synth_bite_report_t synth;
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exciter_bite_report_t exciter;
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aesa_synthetic_report_t aesa_synthetic;
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//aesa_bite_report_t aesa;
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};
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//#]
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//#[ type cdp_bite_status_t
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struct cdp_bite_status_t
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{
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enum rf_fails_codes_t
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{
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rf_stc_fail=(1<<0),
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rf_nagc_fail=(1<<1)
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};
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cdp_bite_phase_t phase;
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unsigned int validity;
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unsigned int rf_fails;
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unsigned int cal_fails;
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unsigned int ch_fails;
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unsigned int rf_group_fails;
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unsigned int spare[4];
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};
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//#]
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//#[ type cdp_rf_bite_report_t
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struct cdp_rf_bite_report_t
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{
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unsigned int stc_valid;
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unsigned int stc_fail[5][3]; //4 acq ch x 3 rf ch + 1 ac channel where to merge all the other fails
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unsigned int nagc_valid;
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unsigned int nagc_report[4];
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unsigned int spare[7];
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};
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//#]
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//#[ type cdp_cal_bite_report_t
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struct cdp_cal_bite_report_t
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{
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unsigned int valid;
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unsigned cal_fail[16];
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unsigned int spare[8];
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};
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//#]
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//#[ type cdp_version_info_t
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struct cdp_version_info_t
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{
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unsigned int valid;
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char ver[8];
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char fpga[2][8];
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};
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//#]
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//#[ type cdp_bite_graph_info_t
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struct cdp_bite_graph_info_t
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{
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unsigned int valid;
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uint8_t graph[3][128];
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};
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//#]
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#endif
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//;;Rpy:: end
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