81 lines
1.0 KiB
INI
81 lines
1.0 KiB
INI
[default]
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port=50069
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ip="192.168.2.101"
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smart=1
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section=APP1
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srio_base=$0x500000
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fpga_base=$0x0
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fpga_sector=0x010000
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[TGT-0]
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appName=EIF/FPGA0
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description="SATA"
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slotAddress=$0x13
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arch=Xilinx
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name=EIF/FPGA0
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section=
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filePrefix=FPGA-
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addressStartArea
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[TGT-1]
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appName=EIF/FPGA1
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description="?"
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slotAddress=$0x73
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arch=Xilinx
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name=EIF/FPGA1
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section=
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filePrefix=FPGA-
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[TGT-2]
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appName=XIF1/FPGA0
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description="?"
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slotAddress=$0x14
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arch=Xilinx
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name=XIF1/FPGA0
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section=
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filePrefix=FPGA-
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[TGT-3]
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appName=XIF1/FPGA1
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description="?"
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slotAddress=$0x74
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arch=Xilinx
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name=XIF/FPGA1
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section=
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filePrefix=FPGA-
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[TGT-4]
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appName=XIF2/FPGA0
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description="?"
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slotAddress=$0x15
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arch=Xilinx
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name=XIF2/FPGA0
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section=
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filePrefix=FPGA-
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[TGT-5]
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appName=XIF2/FPGA1
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description="?"
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slotAddress=$0x75
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arch=Xilinx
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name=XIF2/FPGA1
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section=
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filePrefix=FPGA-
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[TGT-6]
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appName=DFE/FPGA0
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description="Core FPGA"
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slotAddress=$0x16
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arch=Xilinx
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name=DFE/CoreFPGA
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section=
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filePrefix=FPGA-DFE
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[TGT-7]
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appName=DFE/FPGA1
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description="spare"
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slotAddress=$0x76
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arch=Xilinx
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name=DFE/FPGA1
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section=
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filePrefix=FPGA- |