146 lines
1.9 KiB
INI
146 lines
1.9 KiB
INI
[default]
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port=50069
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ip="192.168.2.102"
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smart=1
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section=APP1
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srio_base=$0x500000
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fpga_base=$0x0
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fpga_sector=0x010000
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defTarget=AESA_RFIF
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[MODEL-0]
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idModel=0
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model=xcku040
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description=128Mbit xcku040
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type=0
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3_4Byte=0
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numSector=256
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goldenAddressStartArea=0x00000000
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goldenAddressStopArea=0x007FFFFF
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userAddressStartArea=0x00800000
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userAddresStopArea=0x00FFFFFF
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[MODEL-1]
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idModel=1
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model=xcku060
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description=128Mbit xcku060
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type=1
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3_4Byte=1
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numSector=512
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goldenAddressStartArea=0x00000000
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goldenAddressStopArea=0x00FFFFFF
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userAddressStartArea=0x01000000
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userAddresStopArea=0x01FFFFFF
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[MODEL-2]
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idModel=2
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model=rfif
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description=256Mbit
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type=1
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3_4Byte=1
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numSector=512
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goldenAddressStartArea=0x00000000
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goldenAddressStopArea=0x003FFFFF
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userAddressStartArea=0x00400000
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userAddresStopArea=0x007FFFFF
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testAddress=0x01F00000
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[TGT-0]
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idTgt=EIF_FPGA1
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description=EIF FPGA1 0x13
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slotAddress=0x13
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arch=Xilinx
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name=EIF_FPGA1
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filePrefix=EIF_FPGA1
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idModel=0
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[TGT-1]
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idTgt=EIF_FPGA2
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description=EIF FPGA2 0x73
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slotAddress=0x73
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arch=Xilinx
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name=EIF_FPGA2
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filePrefix=EIF_FPGA2
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idModel=0
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[TGT-2]
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idTgt=XIF1_FPGA1
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description=XIF1/FPGA1 0x14
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slotAddress=0x14
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arch=Xilinx
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name=XIF1_FPGA1
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filePrefix=XIF1_FPGA1
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idModel=0
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[TGT-3]
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idTgt=XIF1_FPGA2
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description=XIF1/FPGA2 0x74
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slotAddress=0x74
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arch=Xilinx
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name=XIF1_FPGA2
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filePrefix=XIF1_FPGA2
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idModel=0
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[TGT-4]
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idTgt=XIF2_FPGA1
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description=XIF2/FPGA1 0x15
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slotAddress=0x15
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arch=Xilinx
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name=XIF2_FPGA1
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filePrefix=XIF2_FPGA1
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idModel=0
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[TGT-5]
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idTgt=XIF2_FPGA2
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description=XIF2/FPGA2 0x75
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slotAddress=0x75
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arch=Xilinx
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name=XIF2_FPGA2
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filePrefix=XIF2_FPGA2
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idModel=0
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[TGT-6]
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idTgt=DFE_FPGA1
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description=DFE/FPGA1 0x16
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slotAddress=0x16
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arch=Xilinx
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name=DFE_FPGA1
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filePrefix=DFE_FPGA1
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idModel=1
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[TGT-7]
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idTgt=DFE_FPGA2
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description=DFE/FPGA2 0x76
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slotAddress=0x76
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arch=Xilinx
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name=DFE_FPGA2
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filePrefix=DFE_FPGA2
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idModel=0
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[TGT-8]
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idTgt=AESA_RFIF
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description=AESA/RFIF 0x16
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slotAddress=0x16
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arch=RFIF
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name=AESA_RFIF
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filePrefix=AESA_RFIF
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idModel=2
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